PCB Via Current Capacity & Array Sizing Calculator
Based on IPC-2152 and IPC-2221 thermal models, calculate single via current carrying capacity, DC resistance, and parasitic inductance. Input your target circuit current to calculate the minimum number of parallel vias required with thermal cluster derating.
Core Fact: On a standard 1.6 mm FR-4 PCB, a 0.3 mm (12 mil) drill via with 20 μm barrel plating carries 1.2A ~ 1.5A safely at ΔT = 10°C, with a DC resistance of ~1.2 mΩ.
Array Rule: When clustering multiple vias for high currents (5A, 10A, 20A), mutual thermal heating necessitates a 0.80 derating factor: N = ⌈ I_target / (I_via × 0.8) ⌉. A 10A line requires at least 9 to 10 vias of 0.3 mm drill diameter.
IPC-2152 Results
| Single Via Max Current Isingle | — A |
| Barrel Copper Area Abarrel | — mil² (— mm²) |
| Single Via DC Resistance Rvia | — mΩ |
| Single Via Inductance Lvia | — nH |
| Total Array Parallel Resistance | — mΩ |
| Array Voltage Drop ΔV | — mV |
| Array Total Power Loss | — W |
Formulas (IPC-2152 / 2221)
Acu = π × tcu × (d - tcu)
Isingle = 0.048 × ΔT0.44 × (Amil²)0.725
Rvia = ρT × h / Acu
N = ⌈ Itarget / (Isingle × kderate) ⌉
Standard PCB Via Ampacity Lookup Table (1.6mm Board / 20μm Plating)
| Drill Dia (mm / mil) | Copper Area (mm²) | ΔT = 10°C Max Current | ΔT = 20°C Max Current | DC Resistance (mΩ) | Recommended Continuous Current |
|---|---|---|---|---|---|
| 0.20 mm (8 mil) | 0.0113 mm² | 0.92 A | 1.25 A | 2.44 mΩ | 0.8 A |
| 0.25 mm (10 mil) | 0.0145 mm² | 1.11 A | 1.51 A | 1.91 mΩ | 1.0 A |
| 0.30 mm (12 mil) [Standard] | 0.0176 mm² | 1.29 A | 1.75 A | 1.57 mΩ | 1.2 A |
| 0.40 mm (16 mil) | 0.0239 mm² | 1.61 A | 2.19 A | 1.15 mΩ | 1.5 A |
| 0.50 mm (20 mil) [Power] | 0.0302 mm² | 1.92 A | 2.60 A | 0.91 mΩ | 1.8 A |
| 0.60 mm (24 mil) | 0.0364 mm² | 2.20 A | 2.99 A | 0.76 mΩ | 2.0 A |
| 0.80 mm (32 mil) | 0.0490 mm² | 2.74 A | 3.72 A | 0.56 mΩ | 2.5 A |
| 1.00 mm (40 mil) | 0.0616 mm² | 3.24 A | 4.40 A | 0.45 mΩ | 3.0 A |
Frequently Asked Questions on PCB Via Ampacity (FAQ)
When vias are clustered closely (e.g. under a MOSFET drain pad), adjacent vias act as heat sources for each other. Unlike an isolated single via that dissipates heat into surrounding FR-4 easily, the center vias in a cluster run significantly hotter. An engineering derating factor of 0.75 ~ 0.85 must be applied, with pitch maintained at 1.2mm to 1.5mm in a staggered layout.
Epoxy resin plugging itself has low thermal conductivity (~0.3 W/m·K), but VIPPO allows placing vias directly on component pins (BGA/QFN/power packages). This eliminates horizontal trace length and loop inductance, drastically improving high-speed power delivery.
Drilling hundreds of vias ruins internal ground planes and consumes immense board area. In modern hardware design, surface-mount SMT Copper Busbars or embedded copper blocks are used to route currents up to 300A with milliohm to microohm resistance.
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